Swapnil Sapre has over a decade of verification and validation experience for System Design, ASIC/SOC and IPs. He has been exposed to various verification and Validation techniques and methodologies like Formal Verification, Assertion Based Verification, Constraint Driven Random based and Coverage Driven Verification, VMM,URM,AVM and OVM i.e. Open Verification Methodology. Swapnil has been providing consultation to various organizations through his expertise in - System Verilog, Verilog, and VHDL ,ASIC-SOC-FPGA,Memory,Peripheral verification and System Validation.
Swapnil has worked on the domains like Serial Interface, Wireless, SoC, Avionics and- Processor. Apart from Chip design aspect -Swapnil also work and consults on System Design -Integration, De-buggers, Tools, Scripts, Oscilloscopes, Software Drivers, Linux, DLLs , Applications and Firmware and ROM development.
Swapnil has received recognition from Respected President Of India for his presentation on “Education-Re engineered”, that was a thought paper presentation to uplift the education curriculum, methodology and process for imparting engineers in country...